Method and mechanism for programmable filtering of texture map data in 3D graphics subsystems

ABSTRACT

A system, method and apparatus to provide flexible texture filtering. A programmable texture filtering module is introduced into the graphics processing pipeline of a graphic coprocessor and graphic processor integrated with the host. A program from a defined instruction set may then be loaded into texture processing cores to process texture data consistent with the program.

BACKGROUND

1. Field of the Invention

The embodiments of the invention relate to computer graphics. Morespecifically, embodiments of the invention relate to processing oftexture map data.

2. Background

Graphics applications, and particularly three dimensionally (3D) graphicapplications have long been one of the most processing intensiveactivities performed by personal computers. To improve graphicprocessing capabilities, graphics co-processors have proliferated andare widely available on most modern day personal computers. Graphiccoprocessors are specialized integrated circuits designed to quicklyperform processing intensive tasks required by graphic applications.

The transformation of scene information (source data) into 3D images(display output) requires a number of operations. These operations inaggregate are referred to as a 3D graphics rendering pipeline. Theoperations performed by the pipeline can be grouped into certainfundamental functionalities. One of these functionalities is texturemapping. Texture mapping is a process in which the one, two or threedimensional image representing an object surface properties (such asappearance, reflectivity, or other such properties) is applied to athree dimensional mesh representing the object in a final rendering.While a two dimensional image is most commonly used, otherdimensionalities are possible.

It is frequently the case when a texture image is applied to an objectin a final rendering, there is disparity between a number of sampletexture elements (texels) and the source texture image and the number ofpicture elements (pixels) to which the image is mapped. When the numberof texels in a given range is less than the number of pixels, then thetexture is required to be upsampled. When upsampling a texture, a schememust be used to fill intermediate values. This scheme is referred toherein as “texture filtering” and has largely been performed by a fixedfunction state machine. Most current graphic coprocessor support fourtypes of texture filtering; point sampling, bilinear filtering,trilinear filtering and anisotropic filtering. As the filtering methodsbecome increasingly complex, the state machine required to perform thembecomes increasingly complex and requires increased real estate withinthe graphics coprocessor. This coupled with the fact that uses fortexture data continues to expand, for example, texture data is beingused for lighting and other surface properties in addition to color,renders the commonly employed linear interpolation inefficient or eveninsufficient.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention are illustrated by way of example and notby way of limitation in the figures of the accompanying drawings inwhich like references indicate similar elements. It should be noted thatdifferent references to “an” or “one” embodiment in this disclosure arenot necessarily to the same embodiment, and such references mean atleast one.

FIG. 1A is a block diagram of a system of one embodiment of theinvention.

FIG. 1B is a diagram of texture sampling in one embodiment of theinvention.

FIG. 2 is a flow diagram of the setup of the textured filtering modulein one embodiment of the invention.

FIG. 3 is a flow diagram of texture filtering in one embodiment of theinvention.

DETAILED DESCRIPTION

FIG. 1A is a block diagram of a system of one embodiment of theinvention. A host processor 100 is coupled by a bus 102 to a memory 104.A graphics coprocessor 106 is also coupled to the bus 102. Additionally,graphics coprocessor 106 may be coupled to memory 104 by an acceleratedgraphics port (AGP) 112. The AGP may adhere to Accelerated Graphics PortAGP V3.0 Interface Specification Rev. 1.0 published September 2002(hereinafter the AGP Specification). AGP 112 allows rapid access tographics data residing in memory 104. Also coupled to the bus areframebuffer 108 and display 110. In some embodiments, framebuffer 108may be contained within memory 104. Graphics coprocessor 106 includespixel processing pipeline 120. Within the pixel processing pipeline 120is a vertex processing module 122, primitive assembly module 124, afragment processing module 126 and a framebuffer processing module 128.Vertex processing module 122 in operation receives vertex data, whichmay include, for example, 3D positional information, color informationand other similar information related to vertices in the graphic image.In one embodiment, vertex data is of the form V=X, Y, Z, T_(u), T_(v),RGB. In this expression, X, Y, Z are the three dimensional Cartesiancoordinates of the vertex, T_(u) and T_(v) are the two dimensionalcoordinate of the corresponding texel in the texture map and RGB are thered, green and blue color values at the vertex. Other forms and contentsof vertex data are also contemplated.

Vertex processing module does three-dimensional transformations on 3Dpositional data conveyed, and may, for example, applies lighting. Theprocessed vertices are passed to the primitive assembly module, whichreceives connectivity data. The connectivity data may include indices topermit assembly of primitives, typically triangles, based on thevertices and indices received.

The primitives are passed to the fragment processing module 126 whichprocesses the primitives to identify fragments and apply texture data tobuild an output. As used herein, “fragment” refers to a pixel or groupof contiguous pixels that are to be consistently processed to generatethe output. The fragment processing exchanges data relating to texturemapping the fragments with a texture filter module 130.

The texture filter module 130 communicates with fragment processingmodule 126 to supply texels for application to the pixels. In oneembodiment, texture filter module 130 is programmable. In this context,programmable is deemed to mean capable of executing a software programconsisting of one or more instructions from a defined instruction set.One example of an instruction set is set forth below in Table 1. TABLE 1Instruction Description ADD A, B Adds A and B operands SUB A, BSubtracts B from A MUL A, B Multiples A by B RCP A, B Makes A thereciprocal of B CMP A, B, X Compares A, B according to immediate X,places result in A MIN A, B Compares A, B leaves minimum of two valuesin A MAX A, B Compares A, B leaves maximum of two values in A MOV A, BMoves B into A

Alternative instruction sets, either shorter or longer, may be employedin various embodiments of the invention.

In one embodiment, texture filter module 130 includes a plurality oftexture processing cores (TPCs) 132 (16 TPC are shown in FIG. 1). Otherembodiments may have more or fewer TPCs. In one embodiment, a single TPCexists. In one embodiment, each TPC 132 is capable of processing a pixelin parallel with each of the other TPC 132. Each core 132 may beprovided with a register set 134 which may include various types ofregisters such as control registers, source registers, temporaryregisters and an output register.

In one embodiment, the control registers include a sampling register, astatus register, an address register, an offset register, and aplurality of fraction registers. In one embodiment, the samplingregister has one bit corresponding to each source registers indicatingwhether the source register should be sampled or not. For example, ifthere are sixteen source registers, the sampling register may be asixteen bit register with one bit corresponding to each of the sixteensource registers. In one embodiment, the status register is used toindicate the status of the TPC after certain conditions, such asoverflow, divide by zero, etc. In one embodiment, the address registermay be a 32 bit register containing the address of the texture map data.In one embodiment, this register may be accessible only by anapplication programming interface (API) rather than providing directaccess to a programmer. The offset register may be used to provide anoffset into the texture data corresponding to the nearest texelcoordinate. Fraction registers may be used to hold the fractionalcoordinate between the texel samples in each dimensionality. In oneembodiment, these would be provided by the fragment processing module126. In one embodiment above, where V=X, Y, Z, T_(u), T_(v), RGB; T_(u)and T_(v) correspond to a pixel to be texture mapped would be providedto the texture filtering module. As one example, an eight pixel onedimensional texture coordinate of 0.175 would fall between the second(0.125) and third (0.25) texel. It would equate to a fraction of 0.2.The fraction in this embodiment is found as (0.175−0.125)/0.125 or moregenerally, the coordinate less the closest lower increment divided bythe increment value.

FIG. 1B is a diagram of texture sampling in one embodiment of theinvention. In one embodiment, sixteen source registers are provided.With each register corresponding to one texel in a 4×4 grid surroundingthe T_(u)T_(v) sampling location of the texture sample point and wouldcorrespond to pixels addressed in such a fashion. While T_(u)T_(v) mappsto a location between texels 5 and 6 and texels 9 and 10, thecontribution of the sixteen texels in the patch to the texture valueassigned to T_(u)T_(v) may be defined by the texture filtering program.In some embodiments, only texels 5, 6, 9 and 10 provide a contribution.In other embodiments, all sixteen texels may contribute. In still otherembodiments, all diagonal prixels in the group may contribute. Asillustrated, the programmable nature of the texture filtering modulepermits robust and flexible texture filtering options.

Temporary registers may be provided for optional use by a programmerperforming intermediate calculations on sample data. An output registeris provided to store the output once the filtering operation iscomplete. In one embodiment, a 32 bit register is provided to receivethe final result. Larger registers may be employed, however, in someembodiments a 32 bit ARGB (alpha red green blue) value is deemedsufficient.

The actual filtering may be performed by the texture filtering module130 by loading a desired filtering program into a textured processingcore. The filtering program corresponds to a fragment to be processed.Within a region of an image, it may be desirable to apply variouseffects to the texture data accordingly. Thus, for a particular graphicimage, there may be numerous filtering programs employed. For example,the filter program applied to a shiny part of a leather jacket on animage would likely to be different than the filter program applied to ascuffed part of a leather jacket. By using different programs in etexture filter module, the different effect can be accommodated. Theusage of several filter programs during the course of rendering a givenscene image is analogous to how, under the current-day fixed-functionschemes, the rendering of a given scene may involve switching betweenthe different fixed-function filtering states for different parts of thescene.

The program employed will influence which of the e.g. 16 texels areactually sampled to perform the texture filtering. In one embodiment,texture data may be arranged in memory to optimize access to the texelslikely to be sampled. For example, if the sampling register indicatesevery fourth texel value is active, the texture data may be stored sothat points 1, 5, 9 and 13 are contiguous in memory, points 2, 6, 10,etc. are contiguous. As another example, where every second texel isactive, 1, 3, 5, 7, etc. are contiguous and 2, 4, 8, etc. arecontiguous. This arrangement in memory may be performed by the hostprocessor 100 or the graphic coprocessor 106.

Arranging memory requires a certain amount of processor resources, inone embodiment, a determination is made when the likely use of thetexture data exceeds a threshold cost required to rearrange it. Thus,where the usage of the textured data justifies the cost to rearrange it,in one embodiment, the textured data is rearranged in memory tofacilitate access. The threshold may be selected based on objectiveguidelines such as number of texels to be processed with a givenprogram.

Once texture filtering is complete and the output generated, the outputvalue may then be passed back to fragment processing module 126 topermit the output fragment to be built. The output built by the fragmentprocessing module 126 is passed to framebuffer processing module 128.Framebuffer processing module 128 combines the pixels received with theexisting framebuffer for output to display 110.

FIG. 2 is a flow diagram of the setup of the textured filtering modulein one embodiment of the invention. At functional block 202, a texturefilter program is loaded into a texture processing core of the texturefiltering module. At functional block 204, the sampling register isinitialized to indicate the texels surrounding a sample point that willbe sampled as part of the filtering process. At decision block 206, adetermination is made if the texels to be sampled in conjunction withthe number of samplings required justify reorganization of the texturedata in memory. If so, the texture data is reordered for efficientaccess at functional block 208. After reordering, or if no reordering isrequired, the address register is initialized at functional block 210.

FIG. 3 is a flow diagram of texture filtering in one embodiment of theinvention. At functional block 302, the texture filter fetches thecoordinate data for pixels to be rendered from the vertex pipeline. Inone embodiment, these will be fetched from the fragment processingmodule. At functional block 304, texel values identified from thesampling register are fetched from memory. At functional block 306,fraction registers are loaded with the coordinate data. The textureprocessing cores are used to execute a filter program at functionalblock 308. At decision block 310, a determination is made if theexecution of the filter program necessitates setting of a status flag.If the execution requires the status flag such as a divide by zero oroverflow, the status register is loaded with an appropriate value atfunctional block 312. If no status flag is required, or after the statusregister has been loaded, the output value is loaded into the outputregister and the output is signaled to be available at functional block314. At decision block 316, a determination is made if there are morepixels to be rendered using the existing filter program. If so, a flowcontinues. If not, it ends.

Although the above flow diagrams are arranged in a particular order, itshould be understood that some of the operations may be performed inparallel or in a different order than depicted. Accordingly, suchparallization or rearrangement is within the scope and contemplation ofthe embodiments of the invention. It should also be noted that while inonly one embodiment, a single texture processing core may be present inthe texture filter module, embodiments with multiple texture processingcores, pixels may be processed in parallel with each core following theflow depicted in FIG. 3.

In the foregoing specification, the invention has been described withreference to specific embodiments thereof. It will, however, be evidentthat various modifications and changes can be made thereto withoutdeparting from the broader spirit and scope of the invention as setforth in the appended claims. The specification and drawings are,accordingly, to be regarded in an illustrative rather than a restrictivesense.

1. A method comprising: fetching coordinate data for a pixel to berendered; fetching texel values corresponding to the pixel; filteringthe texel values through a programmable filter; and outputting afiltered texture value for the pixel.
 2. The method of claim 1 whereinfiltering texel values comprises: reading a control register; and usingat least one location specified in the control register as a sourcelocation.
 3. The method of claim 1 wherein fetching coordinate datacomprises: retrieving X, Y, Z coordinate data from a vertex pipeline. 4.The method of claim 1 further comprising: writing coordinate fractiondata to a plurality of registers.
 5. The method of claim 1 whereinoutputting comprises: writing the filtered texture value to a register;and signaling a processor that the filtered texture value is available.6. An apparatus comprising: a fragment processing module; a programmabletexture filtering module in communication with the fragment processingmodule to programmably filter texture data corresponding to at least onepixel; and a frame buffer processing module to combine filtered texturedata with an existing frame buffer.
 7. The apparatus of claim 6 whereinthe programmable texture filtering module comprises: a plurality ofcontrol registers; a plurality of source registers; a plurality oftemporary registers; and at least one output register.
 8. The apparatusof Clam 7 wherein the source registers are read only.
 9. The apparatusof claim 7 wherein the plurality of control registers comprises: astatus register; an address register; an offset register; and aplurality of fraction registers.
 10. The apparatus of claim 7 where theplurality of the control registers comprise: at least one samplingregister have a bit corresponding to each of the source registers toindicate if sampling of a corresponding source register is required. 11.The apparatus of claim 6 wherein the programmable texture filteringmodule comprises: a plurality of processing cores to execute aninstruction set.
 12. The apparatus of claim 6 wherein a subset of theplurality of cores are to execute a filtering program on at least onepixel in parallel.
 13. A system comprising: a memory, a plurality oftexture processing cores (TPC) coupled to the memory to programmablyfilter texture data; a fragment processing module to apply the filteredtexture data to at least one fragment; and a display to display an imagecreated using the at least one fragment.
 14. The system of claim 13wherein the plurality of TPC and the fragment processing module areintegrated with a host processor.
 15. The system of claim 13 wherein theplurality of TPCS and the fragment processing module reside in agraphics coprocessor.
 16. The system of claim 13 comprising: a registerset associated with each TPC of the plurality.
 17. The system of claim15 further comprising: an accelerated graphics port coupling thegraphics coprocessor to the memory.
 18. A computer readable storagemedia containing executable computer program instructions which whenexecuted cause a digital processing system to perform a methodcomprising: fetching coordinate data for a pixel to be rendered;fetching texel values corresponding to the pixel; filtering the texelvalues through a programmable filter; and outputting a filtered texturevalue for the pixel.
 19. The computer readable storage media of claim 18which when executed cause a digital processing system to perform amethod further comprising: reading a control register; and using atleast one location specified in the control register as a sourcelocation.
 20. The computer readable storage media of claim 18 which whenexecuted cause a digital processing system to perform a method furthercomprising: retrieving X, Y, Z coordinate data from a vertex pipeline.21. The computer readable storage media of claim 18 which when executedcause a digital processing system to perform a method furthercomprising: writing coordinate fraction data to a plurality ofregisters.
 22. The computer readable storage media of claim 18 whichwhen executed cause a digital processing system to perform a methodfurther comprising: writing the filtered texture value to a register;and signaling a processor that the filtered texture value is available.